1. Field of the Invention
The present invention relates to a silicon single crystal wafer having few crystal defects, as well as to a method for producing it.
2. Description of the Related Art
Along with a decrease in size of semiconductor devices for achieving an increased degree of integration of semiconductor circuits, more severe quality requirements have recently been imposed on silicon single crystals which are grown by the Czochralski method (hereinafter referred to as the CZ method) for use as materials for substrates of semiconductor devices. Particularly, there has been required a reduction in density and size of grown-in defects such as FPDs, LSTDs, and COPs, which are generated during the growth of a single crystal and degrade oxide dielectric breakdown voltage and characteristics of devices.
In connections with the above-mentioned defects incorporated into a silicon single crystal, first are described factors which determine the concentration of a point defect called a vacancy (hereinafter may be referred to as V) and the concentration of a point defect called an interstitial-silicon (hereinafter may be referred to as I).
In a silicon single crystal, a V region refers to a region which contains a relatively large number of vacancies, i.e., depressions, pits, voids or the like caused by missing silicon atoms; and an I region refers to a region which contains a relatively large number of dislocations caused by excess silicon atoms or a relatively large number of clusters of excess silicon atoms. Further, between the V region and the I region there exists a neutral (hereinafter may be referred to as N) region which contains no or few excess or missing silicon atoms. Recent studies have revealed that the above-mentioned grown-in defects such as FPDs, LSTDs, and COPs are generated only when vacancies and/or interstitials are present in a supersaturated state and that even when some atoms deviate from their ideal positions, they do not appear as a defect so long as vacancies and/or interstitials do not exceed the saturation level.
It has been confirmed that the concentration of vacancies and/or interstitials depends on the relation between the pulling rate (growth rate) of crystal in the CZ method and the temperature gradient G in the vicinity of a solid-liquid interface of a growing crystal, and that another type of defect called oxidation-induced stacking fault (hereinafter may be referred to as OSF) is present in ring-shape distribution in the vicinity of a boundary between a V region and an I region, when the cross section vertical to the axis of crystal growth is observed.
When a crystal is pulled through use of a CZ pulling apparatus with a furnace structure (hereinafter occasionaly referred to as hot zone: HZ) having a large temperature gradient G in the vicinity of a solid-liquid interface of the crystal with varying a growing rate from high speed to a low speed along the crystal axis, a defect distribution chart for defects due to crystal growth as shown in FIG. 5 can be obtained.
The defects in the radial cross section can be classified as follows. When the growth rate is relatively high; e.g., about 0.6 mm/min or higher, grown-in defects such as FPDs, LSTDs, and COPs which are believed to be generated due to voids at which vacancy-type points defects aggregate are present at a high density over the entire radial cross section of a crystal. The region where these defects are present is called a "V-rich region" (See FIG. 5(A), line (A) and FIG. 6(A)). When the growth rate is not greater than 0.6 mm/min, as the growth rate decreases the above-described OSF ring is generated from a circumferential portion of the crystal. In such a case, L/D (large dislocation, simplified expression of interstitial dislocation loop) defects such as LSEPDs and LFPDs which are believed to be generated due to dislocation loop are present at a low density outside the OSF ring.
The region where these defects are present is called an "I-rich region" (hereinafter occasionally referred to as L/D region). Further, when the growth rate is decreased to about 0.4 mm/min or less, the above-described OSF ring shrinks to the center of a wafer and disappears, so that the I-rich region spreads over the entire cross section of the wafer (See FIG. 5, line (C), FIG. 6(C)).
Further, there has been recently found the existence of a region, called a N (neutral) region, which is located between the V-rich region and the I-rich region and outside the OSF ring and in which there exists neither defects of FPDs, LSTDs and COPs stemming from voids nor defects of LSEPDs and LFPDs stemming from a dislocation loop. The region has been reported to be located outside the OSF ring, and substantially no oxygen precipitation occurs there when a single crystal is subjected to a heat treatment for oxygen precipitation and the contrast due to oxide precipitates is observed through use of an X-ray beam. Further, the N-region is on an I-rich region side, and is not rich enough to cause formation of LSEPDs and LFPDs (See FIG. 5, line (B), FIG. 6(B)).
It is proposed that the N-region that is present only partly in the wafer when using a conventional CZ pulling apparatus can be expanded by improving temperature distribution in the furnace of the pulling apparatus, controlling a pulling rate so that V/G value may be 0.20-0.22 mm.sup.2 /.degree. C..multidot.min, in which V is a pulling rate (mm/min), and G is an average intra-crystal temperature gradient (.degree. C./mm) along the pulling direction from a melting point of silicon to 1300.degree. C. (.degree. C./mm) in the entire surface of the wafer and in full length of the crystal (Japanese Patent Application Laid-open (kokai) No. 8-330316).
However, for producing such a single crystal that the region having a very low defect density is expanded to the entire crystal, the producing condition should be controlled in a very narrow range, since the region is limited to the N-region on the side of I-rich region. Particularly, not in a test machine but in a machine for actual production, it is difficult to control precisely, and therefore, there is a problem in productivity, and such a method is not practical.
In a current method of general silicon single crystals, when the growing rate is intentionally changed along the crystal axis from high speed to low speed as shown in FIG. 5, the following types of crystals can be obtained as shown in FIG. 6: (A) crystals having V-rich region in the entire cross section, (B) crystals having both V-rich region and N-region, (C) crystals having I-rich region in the entire cross section (occasionally referred to as L/D rich region type crystal) and (D) crystals having both V-rich region and I-rich region (not shown). Therefore, the growing rate is controlled along the crystal axis to produce a crystal having a quality suitable for intended uses.
The crystals of the type (A) are mass-produced as standard products. The crystal of the type (B), namely V-N coexistent type crystals are produced as improved products of the crystals of the type (A). However, in a device process, yield is low in V-rich region although high in N-region. Accordingly, the crystal of the type (B) is not completely improved. The crystals of the type (C), wherein the entire cross section is occupied by I-rich region are produced as a particle monitor. However, it is not used for fabrication of device, since L/D is detrimental.
The wafers of the types (A), (C) and (D) have a problem that the device yield is lowered by influence of large vacancies, interstitial dislocations or the like remaining on the surface of the wafers when they are used in a device process.
Recently, crystals of type (E) wherein the entire cross section is occupied by N-region (not shown) are proposed. However, they are not practical, since productivity thereof is low. There are also proposed crystals of type (F) wherein the entire cross section is occupied by N-region and OSF ring is generated when being subjected to thermal oxidation or nuclei of OSF ring are present, and neither FPD nor L/D is present in the entire cross section (Japanese Patent Application No. 9-325428). However, there may be present vacancy defects which are finer than FPD. Such defects are detected with Cu decoration. They may cause degradation of oxide dielectric breakdown voltage, and require further improvement.